International Workshop on Smart Networks, Data Processing and Infrastructure Units
May 25, 2023
Hamburg, Germany
Held in conjunction with:
In recent years, the use of smart network adapters, also known as SmartNICs, has seen a rapid increase. These adapters offer new capabilities for high-performance computing (HPC) beyond standard packet processing. Examples include data processing units (DPUs) or infrastructure processing units (IPUs) that have evolved into system-on-a-chip’s (SoCs) that can include programmable FPGAs, lightweight processing cores and specialized accelerators. DPUs are primarily used for data center operations such as packet filtering, I/O acceleration and security, but there is also growing interest in using them to accelerate HPC applications by offloading communication, I/O management and even part of the application computational workload to them.
This workshop brings together experts from the HPC community, including representatives from national laboratories, HPC vendors and international research centers, to share their knowledge and insights on how DPUs can be leveraged to accelerate HPC applications. In addition to presentations on current research and developments, participants will also discuss new trends in DPU design and their potential use cases. Presenters include researchers, tools developers and HPC users, with a keynote speaker to provide an overview of the evolution of SmartNICs and why they are becoming increasingly important in today’s computing landscape.
Topics
The workshop topics will include but not be limited to the following:
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Application use-cases for Data Processing Units
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Programming Interfaces
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Tools that leverage Data Processing Units
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Storage infrastructure opportunities
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Latest DPUs from multiple vendors
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HPC Users, Programmers, Practitioners interested in sharing their experience with DPUs
Workshop Organizers
Rich Graham
NVIDIA
Philip Roth
ORNL
Dirk Pleiter
KTH
Oscar Hernandez
ORNL
Estela Suarez
JSC
Program Committee Members
Gilad Shainer
NVIDIA
Jeff Young
Georgia Tech
Nick Malaya
AMD
Tom Papatheodore
ORNL
Steve Poole
LANL
Filippo Spiga
NVIDIA
View Agenda
Time | Duration | Description | Speaker | Slides |
09:00-9:30 | 30 min | Welcome and Invited Talk: Smart Networks in HPC An Architecture Perspective Challenges and Opportunities | Martin Schulz, Technical University of Munich | Talk |
DPU Efforts Around the World (Vendors) | ||||
09:30-10:00 | 30 min | A Deep Dive into DPU Computing – Addressing HPC/AI Performance Bottlenecks | Gilad Shainer, NVIDIA | Talk |
10:00-10:30 | 30 min | Getting data where it’s needed – potential for CPU, GPU, accelerators, and smart networks | Sam Antao, AMD | Talk |
Efforts Around the World (Use-cases) | ||||
10:30-11:00 | 30 min | Intelligent algorithms on intelligent networks—experiences and challenges using NVIDIA’s BlueField technology | Tobias Weinzierl, Durham University / TUM | Talk |
11:00- 11:30 | Coffee Break | |||
11:30-12:00 | 30 min | Principles and practice of algorithm design on DPU systems | Rich Vuduc, Georgia Institute of Technology |
Talk |
12:00-12:30 | 30 min | Co-Design with DPUs | Ryan Grant, Queen’s University |
Talk |
12:30-13:00 | 30 min | sPIN: in-network high-performance low-power packet processing | Timo Schneider, ETHZ | Talk |
13:00 | Closing Remarks / Adjourn |
Oak Ridge National Laboratory is managed by UT-Battelle for the US Department of Energy